Field of the Invention
The present invention relates to an image forming apparatus which performs power saving control, a control method therefor, and a storage medium.
Description of the Related Art
When an image forming apparatus is powered on, the printer or scanner is started up, power is fed to the board on which the CPU is mounted, and the ASIC is initialized. When the user does not immediately use each device, however, the standby time period increases, thus wasting power. For this reason, conventional image forming apparatuses have been designed to achieve power saving by, for example, stopping power feeding or clock supply (to be referred to as clock gating hereinafter) during periods of non-use of the printer, scanner, various types of boards, and ASIC.
Japanese Patent No. 5578811 discloses an information processing apparatus having a method for establishing synchronization between modules A and B in an ASIC. More specifically, according to the proposed method, when the startup of module B finishes, clock gating is enabled, whereas when the startup of module A finishes, the clock gating of module B is disabled. Assume that module A is a CPU, and module B is an image processing processor. In this case, when clocks are supplied to the CPU and the image processing processor to start up the image processing processor first, clock gating is enabled. When the CPU is started up afterward, the clock gating of the image processing processor, which has been started up first, is disabled. However, the clock gating may be disabled even at the timing when the user does not use the processor. For example, the clock gating may be disabled even when the user does not use the image processing processor immediately after its startup, resulting in an increase in power consumption during standby periods.
The related art described above, however, has the following problem. According to the above related art, when the ASIC as the image processing processor is energized to complete register setting, the clock gating of the ASIC is disabled to set it in an operable state, thus consuming power even during non-use periods. Assume that the ASIC is not energized for power saving during periods other than use periods. In this case, when the ASIC is energized, it is necessary to perform register setting. Because a register setting time period requires, for example, about several hundred ms, it takes time until the operable state is set. This results in a deterioration in performance concerning, for example, image processing such as FCOT (First COpy Time).